Exposure to large and sudden electrostatic discharge (ESD) is a well-known cause of failure for electronic integrated circuits. The discharge may cause significant damage to the integrated circuit by way of dielectric breakdown of oxides and other thin films and by high levels of conduction through relatively small areas of the circuit arising from reverse breakdown of p-n junctions in the circuit. This is particularly true of circuit portions such as buffer circuits, which are connected to power supplies and receive various voltages during operation.
FIG. 1 illustrates a prior art output buffer circuit, which includes ESD protection, of an integrated circuit. As shown, an input/output pad IOPAD1 is connected between a pull up circuit UP1 and a pull down circuit DOWN1 of an output buffer circuit 2. The input/output pad IOPAD1 is also connected to internal logic or other internal circuitry of the integrated circuit via a first resistor R1 of the output buffer circuit 2 and an input buffer circuit 4. The output buffer circuit 2 receives a signal to be supplied to the input/output pad IOPAD1 from the input buffer circuit 4.
The pull up circuit UP1 and the pull down circuit DOWN1 are connected in series between a power supply line 6 and a ground line 8. The power supply line 6 supplies a power supply voltage VDD received via a power supply pad VDDPAD. The ground line 8 is connected to a ground pad VSSPAD for providing a ground voltage VSS. The pull up circuit UP1 includes a PMOS transistor MP1 connected between the power supply line 6 and the pull down circuit DOWN1. The bulk of the PMOS transistor MP1 is also connected to the power supply line 6, and a gate of the PMOS transistor MP1 receives a pre-drive signal from a pre-charge driver circuit (not shown).
The pull down circuit DOWN1 includes first and second NMOS transistors MN1 and MN2 connected in series between the pull up circuit UP1 and the ground voltage line 8. The bulks of the first and second NMOS transistors MN1 and MN2 are connected to the ground line 8. The gate of the first NMOS transistor MN1 is connected to the power supply line 6 via a second resistor R2, and the gate of the second NMOS transistor MN2 receives the pre-drive signal from the pre-charge driver circuit.
During normal operation, when the pre-drive signal is a logic high voltage, the second NMOS transistor MN2 turns on and the PMOS transistor MP1 turns off. As a result, the pull down circuit DOWN1 conducts and pulls the input/output pad IOPAD1 down to the ground voltage VSS. When the pre-drive signal is a logic low voltage, the second NMOS transistor MN2 turns off and the PMOS transistor MP1 turns on. As a result, the pull up circuit UP1 conducts and pulls the input/output pad IOPAD1 up to the power supply voltage VDD.
During an ESD event, when ESD is received at the input/output pad IOPAD1, for example, the output buffer circuit 2 protects the integrated circuit by passing large current to the ground line 8 using parasitic bipolar transistors formed by the pull down circuit DOWN1. FIG. 2 illustrates a cross sectional view of a semiconductor substrate 12 in which the output buffer circuit 2 of FIG. 1 is formed. FIG. 2 illustrates the doped source and drain regions P1+, P2+, N1+, N2+, and N3+ of the PMOS transistor MP1 and the first and second NMOS transistors MN1 and MN2. More specifically, FIG. 2 shows the parasitic bipolar transistors formed by the pull down circuit DOWN1. As shown, the three parasitic lateral npn bipolar transistors NPN1, NPN2 and NPN3 are formed from the n+ source/drains N1+, N2+ and N3+ of the first and second NMOS transistors MN1 and MN2 and the P-well in which the first and second NMOS transistors MN1 and MN2 are formed.
A large ESD current involves avalanche breakdown, or first breakdown, where the parasitic bipolar transistors NPN1, NPN2 and NPN3 turn on and conduct the ESD current to the ground line VSS. FIG. 3 illustrates a voltage versus current graph in which this first break down occurs at voltage Vt1 and current It1. The hole current generated from the avalanche breakdown, drifting through the effective substrate resistance R4 to the ground line 8, may elevate the substrate potential local to the emitter-base junctions of the parasitic bipolar transistors NPN1, NPN2 and NPN3. The emitter-base junctions of the parasitic bipolar transistors NPN1, NPN2 and NPN3 may then begin to weakly forward bias due to the increase of the local substrate potential. The additional electron current through the parasitic bipolar transistors NPN1, NPN2 and NPN3 acts as seed current to drive a significant increase at the collector-base junction of the parasitic bipolar transistors NPN1, NPN2 and NPN3. This is commonly referred to as a snap back mechanism, and FIG. 3 illustrates this snap back taking place at a snap back voltage Vsp.
At high stress levels, the circuit may then go into thermal or second break down—shown at voltage Vt2 and current It2 in FIG. 3. Here, the device temperature has increased to such a level that thermal carrier generation is high enough to dominate the conduction process. This second breakdown is a positive feedback process that causes device failure because of current localization. Commonly, the current level at which an integrated circuit device undergoes second breakdown is used as a predictor of the device's current handling capabilities under ESD events.
Under the ESD stress condition, the large ESD at the input/output pad IOPAD1 may be transmitted to the gate of the first NMOS transistor MN1 through a current path formed by the PMOS transistor MP1 and the voltage supply line 6. This may turn on the first NMOS transistor MN1, which forms a channel between the source and drain N1+ and N2+ of the first NMOS transistor MN1. Current crowds into this channel instead of flowing through the parasitic bipolar transistors NPN1, NPN2, and NPN3. When the lattice temperature at the edge of the channel becomes high, early device failure occurs due to the gate voltage induced current crowding (GVICC) phenomenon.